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1 ?2016 integrated device technology, inc. revision c, november 10, 2016 general description the 844003i-04 is a 3 differential output lvds synthesizer designed to generate ethernet reference clock frequencies. using a 19.44mhz, 20mhz or 25mhz, 18pf parallel resonant crystal, the following frequencies can be generated based on the settings of four frequency select pins (div_sela[ 1:0], div_selb[1:0]): 625mhz, 622.08mhz, 312.5mhz, 250mhz, 156.25mhz, 125mhz and 100mhz. the 844003i-04 has two output banks, bank a with one differential lvds output pair and ba nk b with two differential lvds output pairs. the two banks have their own dedicated frequency select pins and can be independently set for the frequencies mentioned above. the 844003i-04 uses idt?s 3 rd generation low phase noise vco technology and can achieve 1ps or lower typical rms phase jitter, easily meeting ethernet jitter requirements. the 844003i-04 is packaged in a 32-pin vfqfn package. features ? three lvds outputs on two banks, bank a with one lvds pair and bank b with 2 lvds output pairs ? using a 19.44mhz, 20mhz, or 25mhz crystal, the two output banks can be independently set for 625mhz, 622.08mhz, 312.5mhz, 250mhz, 156.25mhz, 125mhz or 100mhz ? selectable crystal oscillator interface or lvcmos/lvttl single-ended input ? vco range: 490mhz to 680mhz ? rms phase jitter at 125mhz (1.875mhz ? 20mhz): 0.50ps (typical) ? full 3.3v output supply mode ? -40c to 85c ambient operating temperature ? available in lead-free (rohs 6) package ? for functional replacement part use 8t49n241 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 gnd xtal_in xtal_out xtal_sel vco_sel mr gnd nc qa0 nqa0 gnd qb0 nqb0 qb1 nqb1 v ddo_b div_sela1 div_sela0 div_selb1 div_selb0 gnd fb_div oeb oea v dd nc nc v dda v dd nc v ddo_a ref_clk 0 1 0 1 phase detector vco 490-680mhz 0 = 25 (default) 1 = 32 0 0 2 0 1 4 (default) 1 0 5 1 1 8 fb_div osc 0 0 1 0 1 2 (default) 1 0 3 1 1 4 qa0 nqa0 qb0 nqb0 qb1 nqb1 oea div_sela[1:0] div_selb[1:0] fb_div mr oeb vco_sel xtal_sel ref_clk xtal_in xtal_out pullup pulldown:pullup pullup pulldown pullup pulldown pulldown:pullup pulldown pullup block diagram pin assignment 844003i-04 32 lead vfqfn 5mm x 5mm x 0.925mm package body k package top view 844003i-04 datasheet femtoclock ? crystal-to-lvds frequency synthesizer
2 ?2016 integrated device technology, inc. revision c, november 10, 2016 844003i-04 datasheet table 1. pin descriptions note: pullup and pulldown refer to internal input resistors. see table 2, pin characteristics, for typical values. number name type description 1, 7, 13, 22 gnd power power supply ground. 2, 3 xtal_in xtal_out input parallel resonant crystal interface. xtal_o ut is the output, xt al_in is the input. xtal_in is also the overdrive pin if you wa nt to overdrive the crystal circuit with a single-ended reference clock. 4 xtal_sel input pullup crystal select pin. select s between the single-ended ref_clk or crystal interface. has an internal pullup resistor so the crystal interface is selected by default. lvcmos/lvttl interface levels. 5 vco_sel input pullup vco select pin. when low, the pll is bypassed and the crystal reference or ref_clk (depending on xtal_sel setting) are passed directly to the output dividers. has an internal pullup resistor so the pll is not bypassed by default. lvcmos/lvttl interface levels. 6 mr input pulldown active high master reset. when logic high, the inte rnal dividers are reset, (except for 1 state, when the device is configured as a buffer), causing the true outputs qxx to go low and the inverted outputs nqxx to go high. when logic low, the internal dividers and the outputs are enabled. mr has an internal pulldown resistor so the power-up default stat e of outputs and dividers are enabled. lvcmos/lvttl interface levels. 8, 26, 29, 30 nc unused no connect. 9 div_sela1 input pulldown division select pin for bank a. default = low. lvcmos/lvttl interface levels. 10 div_sela0 input pullup division select pin for bank a. default = high. lvcmos /lvttl interface levels. 11 div_selb1 input pulldown division select pin for bank b. default = low. lvcmos/lvttl interface levels. 12 div_selb0 input pullup division select pin for bank b. default = high. lvcmos /lvttl interface levels. 14 fb_div input pulldown feedback divide select. when low (default), the feedback divider is set for 25. when high, the feedback divider is set for 32. lvcmos/lvttl interface levels. 15 oeb input pullup output enable bank b. active high outp ut enable. when logic high, the output pair on bank b is enabled. when logic low, the output pair is in a high- impedance state. has an internal pullup re sistor so the default power-up state of the outputs is enabled. lvcmos/lvttl interface levels. 16 oea input pullup output enable bank a. active high outp ut enable. when logic high, the output pair on bank a is enabled. when logic low, the output pair is in a high- impedance state. has an internal pullup re sistor so the default power-up state of the outputs is enabled. lvcmos/lvttl interface levels. 17 v ddo_b power output power supply pin for bank b outputs. 18, 19 nqb1, qb1 output differential bank b output pair. lvds interface levels. 20, 21 nqb0, qb0 output differential bank b output pair. lvds interface levels. 23, 24 nqa0, qa0 output differential bank a output pair. lvds interface levels. 25 v ddo_a power output supply pin for bank a outputs. 27, 31 v dd power core supply pins. 28 v dda power analog supply pin. 32 ref_clk input pulldown single-ended reference clock input. has an internal pulldown resistor to pull to low state by default. can leave floating if us ing the crystal interface. lvcmos/lvttl interface levels.
3 ?2016 integrated device technology, inc. revision c, november 10, 2016 844003i-04 datasheet table 2. pin characteristics function tables table 3a. output bank a configuration select function table table 3c. oea select function table table 3e. feedback divider configuration select function table table 3b. output bank b configuration select function table table 3d. oeb select function table symbol parameter test conditio ns minimum typical maximum units c in input capacitance 4 pf r pullup input pullup resistor 51 k ? r pulldown input pulldown resistor 51 k ? inputs outputs div_sela1 div_sela0 qa0, nqa0 00 2 0 1 4 (default) 10 5 11 8 input outputs oea qa0, nqa0 0 high-impedance 1 active (default) input fb_div feedback divide 0 25 (default) 132 inputs outputs div_selb1 div_selb0 qb [0:1], nqb[0:1] 00 1 0 1 2 (default) 10 3 11 4 input outputs oeb qb[0:1], nqb[0:1] 0 high-impedance 1 active (default)
4 ?2016 integrated device technology, inc. revision c, november 10, 2016 844003i-04 datasheet table 3f. bank a frequency table inputs feedback divider bank a output divider m/n multiplication factor qa0, nqa0 output frequency (mhz) crystal frequency (mhz) fb_div div_sela1 div_sela0 25 0 0 0 25 2 12.5 312.5 20 0 0 0 25 2 12.5 250 25 0 0 1 25 4 6.25 156.25 24 0 0 1 25 4 6.25 150 20 0 0 1 25 4 6.25 125 25 0 1 0 25 5 5 125 25 0 1 1 25 8 3.125 78.125 24 0 1 1 25 8 3.125 75 20 0 1 1 25 8 3.125 62.5 19.44 1 0 0 32 2 16 311.04 15.625 1 0 0 32 2 16 250 19.44 1 0 1 32 4 8 155.52 18.75 1 0 1 32 4 8 150 15.625 1 0 1 32 4 8 125 15.625 1 1 0 32 5 6.4 100 19.44 1 1 1 32 8 4 77.76 18.75 1 1 1 32 8 4 75 15.625 1 1 1 32 8 4 62.5
5 ?2016 integrated device technology, inc. revision c, november 10, 2016 844003i-04 datasheet table 3g. bank b frequency table inputs feedback divider bank b output divider m/n multiplication factor qbx/ nqbx output frequency (mhz) crystal frequency (mhz) fb_div div_selb1 div_selb0 25 0 0 0 25 1 25 625 25 0 0 1 25 2 12.5 312.5 20 0 0 1 25 2 12.5 250 22.5 0 1 0 25 3 8.333 187.5 25 0 1 1 25 4 6.25 156.25 24 0 1 1 25 4 6.25 150 20 0 1 1 25 4 6.25 125 19.44 1 0 0 32 1 32 622.08 19.44 1 0 1 32 2 16 311.04 15.625 1 0 1 32 2 16 250 18.75 1 1 0 32 3 10.667 200 19.44 1 1 1 32 4 8 155.52 18.75 1 1 1 32 4 8 150 15.625 1 1 1 32 4 8 125
6 ?2016 integrated device technology, inc. revision c, november 10, 2016 844003i-04 datasheet absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operat ion of product at these condit ions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 4a. power supply dc characteristics, v dd = v ddo_a = v ddo_b = 3.3v 10%, t a = -40c to 85c table 4b. lvcmos/lvttl dc characteristics, v dd = v ddo_a = v ddo_b = 3.3v 10%, t a = -40c to 85c item rating supply voltage, v dd 4.6v inputs, v i xtal_in other inputs 0v to v dd -0.5v to v dd + 0.5v outputs, i o continuous current surge current 10ma 15ma package thermal impedance, ? ja 37 ? c/w (0 mps) storage temperature, t stg -65 ? c to 150 ? c symbol parameter test conditio ns minimum typical maximum units v dd core supply voltage 2.97 3.3 3.63 v v dda analog supply voltage v dd ? 0.20 3.3 v dd v v ddo_a, v ddo_b output supply voltage 2.97 3.3 3.63 v i dd power supply current 140 ma i dda analog supply current 20 ma i ddo_a + i ddo_b output supply current 70 ma symbol parameter test conditio ns minimum typical maximum units v ih input high voltage 2 v dd + 0.3 v v il input low voltage -0.3 0.8 v i ih input high current ref_clk, mr, fb_div, div_sela1, div_selb1 v dd = v in = 3.63v 150 a oea, oeb, vco_sel, xtal_sel, div_selb0, div_sela0 v dd = v in = 3.63v 5 a i il input low current ref_clk, mr, fb_div, div_sela1, div_selb1 v dd = 3.465v, v in = 0v -5 a oea, oeb, vco_sel, xtal_sel, div_selb0, div_sela0 -150 a
7 ?2016 integrated device technology, inc. revision c, november 10, 2016 844003i-04 datasheet table 4c. lvds dc characteristics, v dd = v ddo_a = v ddo_b = 3.3v 10%, t a = -40c to 85c table 5. crystal characteristics note: characterized using an 18pf parallel resonant crystal. symbol parameter test conditio ns minimum typi cal maximum units v od differential output voltage 300 400 500 mv ? v od v od magnitude change 50 mv v os offset voltage 1.25 1.35 1.55 v ? v os v os magnitude change 50 mv parameter test conditions mi nimum typical maximum units mode of oscillation fundamental frequency fb_div = 25 19.6 26.5625 27.2 mhz fb_div = 32 15.313 21.25 mhz equivalent series resistance (esr) 50 ? shunt capacitance 7pf
8 ?2016 integrated device technology, inc. revision c, november 10, 2016 844003i-04 datasheet ac electrical characteristics table 6. ac characteristics, v dd = v ddo = 3.3v 5%, t a = -40c to 85c note: electrical parameters are guaranteed ov er the specified ambient operating temper ature range, which is established when th e device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. th e device will meet specifications after thermal equilibrium has been reached under these conditions. note 1: defined as skew within a bank of outputs at the same voltages and with equal load conditions. note 2: defined as skew between outputs at the same supply voltages and with equal load conditions. measured at the output differential cross points. note 3: this parameter is defined in accordance with jedec standard 65. note 4: characterized with div_sel a[1:0] = 11 and di v_selb[1:0] = 11. note 5: characterized with div_sel a[1:0] = 00 and di v_selb[1:0] = 00. note 6: please refer to the phase noise plots. symbol parameter test conditio ns minimum typical maximum units f out output frequency output divider = 1 490 680 mhz output divider = 2 245 340 mhz output divider = 3 163.33 226.67 mhz output divider = 4 122.5 170 mhz output divider = 5 98 136 mhz output divider = 8 61.25 85 mhz t sk(b) bank skew; note 1 25 ps t sk(o) output skew note 2, 3 outputs @ same frequency 50 ps note 2, 3, 4 qb ? 1, outputs @ different frequencies 250 ps note 2, 3, 5 qb = 1, output s @ different frequencies 525 ps t jit(?) rms phase jitter, random; note 6 625mhz, (1.875mhz - 20mhz) 0.34 ps 312.5mhz, (1.875mhz - 20mhz) 0.34 ps 250mhz, (1.875mhz - 20mhz) 0.42 ps 125mhz, (1.875mhz - 20mhz) 0.50 ps 100mhz, (1.875mhz - 20mhz) 0.41 ps t r / t f output rise/fall time 20% to 80% 150 550 ps odc output duty cycle output divider ? 1 48 52 % output divider = 1 44 56 %
9 ?2016 integrated device technology, inc. revision c, november 10, 2016 844003i-04 datasheet typical phase noise at 100mhz typical phase noise at 625mhz 10gb ethernet filter phase noise result by adding a 10gb ethernet filter to raw data raw phase noise data 100mhz rms phase jitter (random) 1.875mhz to 20mhz = 0.41ps (typical) noise power dbc hz offset frequency (hz) ? ? ? 625mhz rms phase jitter (random) 1.875mhz to 20mhz = 0.34ps (typical) noise power dbc hz offset frequency (hz) ? ? ?
10 ?2016 integrated device technology, inc. revision c, november 10, 2016 844003i-04 datasheet parameter measurement information 3.3v lvds output load ac test circuit output skew output rise/fall time rms phase jitter bank skew output duty cycle/pulse width/period 3.3v 5% v dd, v ddo_a, v dda v ddo_b qx nqx qy nqy 20% 80% 80% 20% t r t f v od nqa0, nqb[0:1] qa0, qb[0:1] phase noise mask offset frequency f 1 f 2 phase noise plot rms jitter = area under the masked phase noise plot noise power t sk(b) nqb0 qb0 nqb1 qb1 nqa0, nqb[0:1] qa0, qb[0:1]
11 ?2016 integrated device technology, inc. revision c, november 10, 2016 844003i-04 datasheet parameter measure ment information, continued differential output voltage setup offset voltage setup applications information power supply filtering technique as in any high speed analog circuitry, the power supply pins are vulnerable to random noise. to achieve optimum jitter performance, power supply isolation is r equired. the 844003i-04 provides separate power supplies to isolate any high switching noise from the outputs to the internal pll. v dd, v dda, v ddo_a and v ddo_b should be individually connected to the power supply plane through vias, and 0.01f bypass capacitors should be used for each pin. figure 1 illustrates this for a generic v dd pin and also shows that v dda requires that an additional 10 ? resistor along with a 10 ? f bypass capacitor be connected to the v dda pin. figure 1. power supply filtering crystal input interface the 844003i-04 has been characteri zed with 18pf parallel resonant crystals. the capacitor values shown in figure 2 below were determined using an 18pf parallel resonant crystal and were chosen to minimize the ppm error. figure 2. crystal input interface v dd v dda 3.3v 10 10f .01f .01f xtal_in xtal_out x1 1 8pf parallel crystal c1 27pf c2 27pf
12 ?2016 integrated device technology, inc. revision c, november 10, 2016 844003i-04 datasheet overdriving the xtal interface the xtal_in input can be overdriven by an lvcmos driver or by one side of a differential driver through an ac coupling capacitor. the xtal_out pin can be left floating. the amplitude of the input signal should be between 500mv and 1.8v and the slew rate should not be less than 0.2v/ns. for 3.3v lvcmos inputs, the amplitude must be reduced from full swing to at least half the swing in order to prevent signal interference with the power rail and to reduce internal noise. figure 3a shows an example of the interface diagram for a high speed 3.3v lvcmos driver. this co nfiguration requires that the sum of the output impedance of the driver (ro) and the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the crystal input will a ttenuate the signal in half. this can be done in one of two ways. first, r1 and r2 in parallel should equal the transmission line impedance. for most 50 ? applications, r1 and r2 can be 100 ? . this can also be accomplished by removing r1 and changing r2 to 50 ? . the values of the resistors can be increased to reduce the loading for a slower and weaker lvcmos driver. figure 3b shows an example of the interface diagram for an lvpecl driver. this is a standard lvpecl termination with one side of the driver feeding the xtal_in i nput. it is recommended that all components in the schematics be placed in the layout. though some components might not be used, they can be utilized for debugging purposes. the datasheet specifications are characterized and guaranteed by using a quartz crystal as the input. figure 3a. general diagra m for lvcmos driver to xtal input interface figure 3b. general diagram for lvpec l driver to xtal input interface vcc xtal_out xtal_in r1 100 r2 100 zo = 50 ohms rs ro zo = ro + rs c1 .1uf lvcmos driver xta l _ o u t xta l _ i n zo = 50 ohms c2 .1uf lvpecl driver zo = 50 ohms r1 50 r2 50 r3 50
13 ?2016 integrated device technology, inc. revision c, november 10, 2016 844003i-04 datasheet recommendations for unused input and output pins inputs: lvcmos control pins all control pins have internal pullups and pulldowns; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. ref_clk input for applications not requiring the use of the reference clock, it can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from the ref_clk to ground. crystal inputs for applications not requiring the us e of the crystal oscillator input, both xtal_in and xtal_out can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from xtal_in to ground. outputs: lvds outputs all unused lvds output pairs can be ei ther left floating or terminated with 100 ? across. if they are left floating, we recommend that there is no trace attached. lvds driver termination a general lvds interface is shown in figure 4. standard termination for lvds type output structure requires both a 100 ? parallel resistor at the receiver and a 100 ? differential transmission line environment. in order to avoid any transmission line reflection issues, the 100 ? resistor must be placed as close to the receiver as possible. idt offers a full line of lvds complia nt devices with two types of output structures: current source and voltage source. the standard termination schematic as shown in figure 4 can be used with either type of output structur e. if using a non-standard termination, it is recommended to contact idt and conf irm if the output is a current source or a voltage source type st ructure. in addition, since these outputs are lvds compatible, the amplitude and common mode input range of the input receivers s hould be verified for compatibility with the output. figure 4. typical lvds driver termination 100 ? + 100 differential transmission line lvds driver lvds receiver
14 ?2016 integrated device technology, inc. revision c, november 10, 2016 844003i-04 datasheet vfqfn epad thermal release path in order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the printed circuit board (pcb) wit hin the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in figure 5. the solderable area on the pcb, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. sufficient clearance should be designed on the pcb between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. while the land pattern on the pcb provides a means of heat transfer and electrical grounding from t he package to the board through a solder joint, thermal vias are nece ssary to effectively conduct from the surface of the pcb to the ground plane(s). the land pattern must be connected to ground through thes e vias. the vias act as ?heat pipes?. the number of vias (i.e. ?h eat pipes?) are application specific and dependent upon the package power dissipation as well as electrical conductivity requirement s. thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. it is recommended to use as many vias connected to ground as possible. it is also recommended t hat the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. this is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal la nd. precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. note: these recommendations are to be used as a guideline only. for further informatio n, please refer to the application note on the surface mount assembly of amkor?s thermally/ electrically enhance leadframe base package, amkor technology. figure 5. p.c. assembly for exposed pad thermal release path ? side view (drawing not to scale) solder solder pin pin exposed heat slug pin pad pin pad ground plane land pattern (ground pad) thermal via
15 ?2016 integrated device technology, inc. revision c, november 10, 2016 844003i-04 datasheet schematic example figure 6 shows an example of an 844003i-04 application schematic. in this example, the device is operated at v dd = v ddo _a = v ddo_b = 3.3v. the 18pf parallel resonant 25mhz crystal is used. the c1 and c2 = 27pf are recommended for frequency accuracy. for different board layouts, the c1 and c2 may be slightly adjusted for optimizing frequency accuracy. two examples of lvds for receiver without built-in termination ar e shown in this schematic. figure 6. ics870931i-01 schematic layout example r4 50 c4 0.1uf x1 25mhz c1 27pf + - vddo_a = vddo_b=3.3v c2 27pf r1 10 qa0 c8 0.1uf vddo_a alternate lvds terminat ion ref_clk set logic input to '0' logic control input examples ru2 not install vdd rd2 1k 1 8 p f nqb1 div_sela0 div_sela1 vdda rd1 not install c5 0.1uf vdd r3 33 oea zo = 50 ohm mr + - oeb vdd zo = 50 zo = 50 ohm ru1 1k zo = 50 ohm c6 0.01u set logic input to '1' qb1 nqa0 to logic input pins xtal_sel vco_sel zo = 50 ohm q1 driv er_lvcmos c9 0.1uf to logic input pins u1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 32 31 30 29 28 27 26 25 gnd xtal_in xtal_out xtal_sel vco_sel mr gnd nc div_sela1 div_sela0 div_selb1 div_selb0 gnd fb_div oeb oea vddo_b nqb1 qb1 nqb0 qb0 gnd nqa0 qa0 ref_clk vdd nc nc vdda vdd nc vddo_a r5 50 vdd vdd div_selb1 c7 10uf vddo_b r2 100 vdd=3.3v div_selb0 c3 .1uf
16 ?2016 integrated device technology, inc. revision c, november 10, 2016 844003i-04 datasheet power considerations this section provides information on power dissipa tion and junction temperature for the 844003i-04. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the 844003i-04 is the sum of the co re power plus the analog power plus the power dissipated in the load(s). the following is the power dissipation for v dd = 3.3v + 10% = 3.63v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. ? power (core) max = v dd_max * (i dd_max + i dda_max ) = 3.63v * (140ma + 20ma) = 580.80mw ? power (outputs) max = v ddo_max * i ddo_max = 3.63v * 70ma = 254.1mw total power_ max = 580.80mw + 254.1mw = 834.9mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad direct ly affects the reliability of the device. the maximum recommended junction temperature is 125c. limiting the internal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ? ja * pd_total + t a tj = junction temperature ? ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (e xample calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ? ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 37c/w per table 7 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.835w * 37c/w = 115.9c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depe nding on the number of loaded ou tputs, supply voltage, air flow and the type of board (multi-layer). table 7. thermal resistance ? ja for 32 lead vfqfn, forced convection ? ja vs. air flow meters per second 012.5 multi-layer pcb, jedec standard te st boards 37.0c/w 32.4c/w 29c/w
17 ?2016 integrated device technology, inc. revision c, november 10, 2016 844003i-04 datasheet reliability information table 8. ? ja vs. air flow table for a 32 lead vfqfn transistor count the transistor count for 844003i-04 is: 4058 ? ja vs. air flow meter per second 012.5 multi-layer pcb, jedec standard te st boards 37.0c/w 32.4c/w 29c/w
18 ?2016 integrated device technology, inc. revision c, november 10, 2016 844003i-04 datasheet 32 lead vfqfn package out line and package dimensions
disclaimer integrated device technology, in c. (idt) reserves the right to modify t he products and/or specifications described h erein at any time, without notice, at idt's sole discretion. performance specifications and operating parameters of the described products are determi ned in an independent state and are not guaranteed to perform the same way when installed in customer products. the information contained herein is provided without representation or warr anty of any kind, whether express or impli ed, including, but not limited to, the suit ability of idt's products for any particular pur pose, an implied warrant y of merchantability, or non-infringement of the intellectual property rights of others. this document is presented only as a guide and does not conv ey any license under intellectual property rights of idt or any third parties. idt's products are not intended for use in applications involving extreme environmental conditions or in life support systems o r similar devices where the failure or malfunction of an idt product can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their o wn risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are trademarks or registered trademarks of idt and its subsidiaries in the u nited states and other countries. other trademarks used herein are the property of idt or their respective third party owners. for datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary . copyright ?2016 integrated device te chnology, inc. all rights reserved. tech support www.idt.com/go/support sales 1-800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com/go/sales corporate headquarters 6024 silver creek valley road san jose, ca 95138 usa www.idt.com ordering information table 10. ordering information revision history sheet part/order number marking package shipping packaging temperature 844003AKI-04LF ics403ai04l ?lead-free? 32 lead vfqfn tray -40 ? c to 85 ? c 844003AKI-04LFt ics403ai04l ?lead-free ? 32 lead vfqfn tape & reel -40 ? c to 85 ? c rev table page description of change date a 15 added layout schematic. 6/10/09 b t4a t6 6 6 8 12 13 16 18 absolute maximum ratings - updated input ratings. power supply dc characteristics table - changed i ddo from 55ma max to 70ma max. ac characteristics table - corrected notes. updated overdriving the xtal interface application note. updated lvds driver termination application note. updated power considerations to coincide with i ddo spec change. updated package drawing. 5/2/11 b 1 product discontinuation notice - last time buy expires november 2, 2016. pdn# cq-15-05. 11/5/15 c t10 19 obsolete datasheet per pdn# cq-15-05. ordering information table - deleted tape & reel count and table note. updated datasheet header/footer. 11/10/16

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